Design of Leakage Power Reduced Static RAM using LECTOR
نویسنده
چکیده
The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. LECTOR is a technique for designing CMOS circuits in order to reduce the leakage current without affecting the dynamic power dissipation, which made LECTOR a better technique in leakage power reduction when compared to all other existing leakage reduction techniques. This paper presents the analysis for leakage current in Static RAM implementing LECTOR technique using 45nm technology. Keywords— Low Power, Sub-threshold leakage current, Selfcontrolled LCTs, Transistor stacking, Deep-submicron
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